The present invention relates to a semiconductor design technology, particularly to a semiconductor memory design technology, and more particularly to a technology of processing a Mode Register Set (MRS) command to determine an operation mode of Dynamic Random Access Memory (DRAM).
In general, most semiconductor memory devices, including DRAMs, should determine an operation mode, such as a Column Address Strobe (CAS) Latency (CL), a Burst Length (BL), a Burst Type (BT) or the like, which meets characteristics required for a system. When an MRS command is inputted, the operation mode is determined based on an MRS code applied to an address pin.
The MRS code consists of a combination of address of 1 bit or multiple bits. For example, an address A0-A2 is used to determine a burst length BL2, BL4, or BL8, an address A3 is used to determine a burst type (sequential or interleave), and an address A4-A6 is used to determine a CAS latency CL1.5, CL2, CL2.5, or CL3. In addition, an address A7 is used to determine whether a memory device is in a test mode or a normal mode, and an address A8 is used to determine whether to reset a Delay Locked Loop (DLL).
Once a mode register field is determined, information thereon is kept until it is reset by another MRS command.
FIG. 1 is a block diagram of a general MRS decoder.
Referring to FIG. 1, the general MRS decoder includes a mode register 10 for latching an MRS code ADD<0:16> in response to an MRS command pulse MRSP, and a mode decoder 12 for decoding a latched MRS code MREG<0:16> to determine an operation mode.
To be more specific, when an MRS code ADD<0:16> is inputted via an address pin together with an MRS command, the mode register 10 latches the MRS code ADD<0:16> in synchronism with an MRS command pulse MRSP generated, in response to the MRS command.
The mode decoder 12 then decodes a latched MRS code MREG<0:16> to output an operation mode signal, such as CL, BL, BT, or the like.
In the above-described general MRS decoder, however, when an illegal MRS code is inputted, a semiconductor memory device is malfunctioning. That is to say, the general MRS decoder decodes such an illegal code as it is upon receipt thereof, and thus causes the memory device to operate in an erroneous operation mode.